This application is based upon Japanese Patent Application No. Hei. 11-48221 filed on Feb. 25, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to serial communication techniques, and particular to a serial communication technique applicable to an electronic control unit (ECU) of, for example, a vehicle engine, and further particular to a serial communication method and a serial communication apparatus performing a serial communication between external serial communication apparatus.
2. Related Art
Conventional serial communication apparatus is disclosed in JP A 9-282265. This serial communication apparatus is constructed so that data (message) is bidirectionally serial-communicated between two microcomputers having a relationship of a master and a slave therebetween. For example, a master microcomputer controls principal engine performs controls such as an ignition timing control and a fuel injection control; and a slave microcomputer performs the other supplemental controls such as an A/D (analog-digital) conversion of sensed data by some kinds of sensor, which are needed for the engine control, and a load calculation. Here, according to the conventional serial communication apparatus, the message is sent in synchronization with a serial communication clock. The message communicated between the microcomputers includes A/D converted data, data read from a RAM, and request commands for each of the processes.
In the actual data communication, a process completion signal (EOCT signal in FIG. 6 of the above-described JP) temporally rises to a logically high level in synchronization with a first trailing edge of the clock, and messages stored in each of shift registers are exchanged each other. After the exchange of the message is completed, the clock is stopped, and the process completion signal (EOCT) falls to a logically low level in synchronization with the clock""s stop. After that, the slave microcomputer performs predetermined process such as the A/D conversion or reading RAM data in accordance with the request command in the message received from the master microcomputer, and rises the process completion signal (EOCT) at the point when the process is completed. The master microcomputer judges a condition that the data is prepared to be sent due to the rising the process completion signal (EOCT) to the logically high level, and resets the clock so that next message is sent to the slave microcomputer.
According to the above-described JP A 9-282265, the communication is suspended due to the clock""s stop while the slave microcomputer performed the predetermined process in accordance with the request command (during EOCT=L in FIG. 6 in the JP). Particularly, in the case where it takes long time to process in the slave microcomputer such that when the request from the master microcomputer is the A/D conversion, a suspended time will be prolonged. Therefore, a suspended time, during which the communication is suspected (ended), is prolonged compared to a time during which the communication is performed, and it becomes hard to improve a communication speed. Furthermore, in this conventional apparatus, it is essential to provide a slave response communication line (EOCT line), and therefore it is inconvenience when a structure is simplified.
On the contrary, it would be thought a countermeasure in which the next message (command and data) is sent after a predetermined interval without applying the slave response communication line (EOCT line). That is, after the slave microcomputer receives the message in synchronization with the clock, the slave microcomputer performed predetermined process (the A/D conversion or the writing RAM) in accordance with the request command. After that, the slave microcomputer receives the next message every a predetermined period (interval) (e.g., 40 xcexcs) within which processes of the slave microcomputer is definitely completed. In this case, the master microcomputer sends the next message every the predetermined period 40 xcexcs regardless of the fact whether the slave microcomputer has completed its process or not. Here, whether the process in the slave microcomputer is accurately completed or not is judged from an ID (identification) bit in the message sent from the slave microcomputer.
According to the countermeasure, the slave response communication line (EOCT line) can be omitted, however, it still contains a problem that the communication time is further prolonged compared to the conventional apparatus in JP A 9-282265, because it needs to send the next message after waiting the predetermined interval (40 xcexcm) within which processes of the slave microcomputer is definitely completed.
Furthermore, as another countermeasure, it would be thought that the clock is not ended until the sending of all messages is completed, however, the process in the slave microcomputer may be prolonged when the request command from the master microcomputer includes certain command, which needs long time, such as a reading of the RAM data, a writing of the RAM data or the A/D conversion. Hence, it is difficult to actually apply to a commercial model.
On the contrary, another conventional serial communication apparatus is disclosed in Japanese Granted Patent No. 2719734. According to the another conventional apparatus, a clock communication line, a master data communication line, a slave data communication line, a synchronously initialize request control line and a slave response control line are provided between a master apparatus and a slave apparatus. The master apparatus sends a synchronously initialize request in synchronization with a start of sending of a master data or with a start of receiving of a slave data; and slave apparatus sends a slave response both after receiving the master data and before sending the slave data. However, this apparatus also contains problems such that communication is suspended when the command is processed, and that it needs slave response communication line.
This invention has been conceived in view of the background thus far described and its first object is to improve a communication speed even when it takes long time to perform a process in accordance with a command.
Its second object is to provide a serial communication system having a simple structure.
According to the present invention, a serial communication apparatus comprises: a plurality of registers; a switcher for alternately switching the condition of the registers every a predetermined numbers of serial communication clock; and a communication controller. Here, when serial communication is performed by using one register under the communication condition, a communication controller performs a process based on a process command, which is externally inputted and is received by another register last time, in the another register under the non-communication condition, and outputs a process result in accordance with the process command.
According to the above-described structure, the serial communication is performed by using one register, and at the same time, a process in accordance with a process command received last time is performed and a process result is outputted. Furthermore, when the register is switched after the predetermined number of serial communication clock passes, the process result in accordance with the process command is registered in the register, which has used for performing the serial communication; and the process result having registered before switching is outputted.
In this way, by alternately using a plural of registers, the process command just after being received can be temporally escaped, and a process in accordance with the escaped process command can be performed in the register at which the process command escapes. Therefore, when it takes long time to complete the process corresponding to the process command, it does not need to stop the communication every command. Hence the communication speed can be improved. Furthermore, it is not essential to ascertain whether a preparation of the communication has completed or not every communication corresponding predetermined clocks. Therefore, it does not need to provide a slave response communication line (e.g., the EOCT line in JP A 9-282265), so that the structure can be simplified.
According to another aspect of the present invention, a serial communication apparatus comprises: a first register; a second register; and a communication controller. The communication controller transfers the communication data in a first register to a second register when the first register receives communication data corresponding to a predetermined numbers of serial communication clock, registers a process result in accordance with the process command included in the communication data into the second register, transfers the process result in the second register to the first register after the predetermined numbers of serial communication clock passes, and registers communication data received after the predetermined numbers of serial communication clocks passes into the second register.
According to the above-described structure, at the second register, after receiving the communication data corresponding to a predetermined numbers of serial communication clock, a process in accordance with the command data included in the communication data is performed and a process result thereof is registered. After the predetermined numbers of serial communication clock passes, the process result in the second register is transferred to the first register and the next communication data is registered in the second register. The present invention according to another aspect can be achieved the same result as the above-described present invention.